1. Field of the Disclosure
Generally, the present disclosure relates to the field of integrated circuits and semiconductor devices and, more particularly, to flash memory cells.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors (FETs), wherein, for many types of complex circuitry, metal-oxide-semiconductor (MOS) technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of N-channel transistors and P-channel transistors are formed on a substrate including a crystalline semiconductor layer.
Although significant advantages may be obtained with respect to performance and controllability of sophisticated planar transistor architectures, in view of further device scaling, new transistor configurations have been proposed in which a “three-dimensional” architecture may be provided in an attempt to obtain a desired channel width, while at the same time maintaining superior controllability of the current flow through the channel region. To this end, so-called FinFETS have been proposed in which a thin sliver or fin of silicon may be formed in a thin active layer of an SOI (semiconductor-on-insulator) substrate, wherein at least on both sidewalls of the fin, and possibly on a top surface thereof, a gate dielectric material and a gate electrode material may be provided, thereby realizing a “double gate” or “tri-gate” transistor, the channel region of which may be fully depleted. Typically, in sophisticated applications, the width of the semiconductor, e.g., silicon, fins is on the order of 10-20 nm and the height thereof is on the order of 30-40 nm. Thus, FinFET transistor architectures, which may also be referred to herein as multiple gate transistors, may provide advantages with respect to increasing the effective coupling of the gate electrode to the various channel regions without requiring a corresponding reduction in the thickness of the gate dielectric material. Moreover, by providing this non-planar transistor architecture, the effective channel width may also be increased so that, for given overall transistor dimensions, an enhanced current drive capability may be accomplished. For these reasons, great efforts have been made in order to provide enhanced transistor performance on the basis of non-planar transistor architectures.
It is noted that both planar and three-dimensional transistor devices can be formed according to the replacement gate approach or the gate first approach. In the replacement gate technique, a so-called “dummy” or sacrificial gate structure is initially formed and remains in place as many process operations are performed to form the device, for example, the formation of doped source/drain regions, performing an anneal process to repair damage to the substrate caused by the ion implantation processes and to activate the implanted dopant materials. At some point in the process flow, the sacrificial gate structure is removed to define a gate cavity where the final HKMG gate structure for the device is formed. Using the gate first technique, on the other hand, involves forming a stack of layers of material across the substrate, wherein the stack of materials includes a high-k gate insulation layer (with a dielectric constant k larger than 5), one or more metal layers, a layer of polysilicon, and a protective cap layer, for example, silicon nitride. One or more etching processes are performed to pattern the stack of materials to thereby define the basic gate structures for the transistor devices. Formation of an e-fuse in accordance with the present disclosure can be readily integrated in both the replacement gate process flow and gate first process flow.
On the other hand, increasingly, non-volatile flash memory cells may have to be incorporated in sophisticated semiconductor devices, wherein the flash memory technique represents one promising technology, in which MOS technology may be efficiently applied to forming storage cells. To this end, basically, a field effect transistor is provided, in which transistor operation is controlled, on the other hand, by a gate electrode, as discussed above, which additionally includes a floating gate that is electrically insulated from the control gate electrode and from the channel region and drain region of the field effect transistor. The floating gate represents a dielectric charge storage region within the control gate electrode of the field effect transistor and may hold stationary charge carriers, which in turn influence the current flow behavior of the field effect transistor. The stationary charge carriers in the floating gate may be injected upon establishing a specific operation mode, which is also referred to as programming of the memory cell, in which per se negative effects, such as hot carrier injection and the like, that is, any type of leakage current generating mechanism, may result in the incorporation of charge carriers in the charge storage region. Consequently, in the normal operation mode, the injected charge carriers in the charge storage region may thus significantly affect the current flow through the channel region of the transistor, which may be detected by appropriate control circuitry. On the other hand, upon erasing the memory cell, the charge carriers in the charge storage region may be removed, for instance by establishing appropriate voltage conditions, thereby establishing a detectable different operational behavior of the field effect transistor during the normal operation mode, i.e., during the operation with the standard supply voltages.
Although the concept of flash memory cells, i.e., of field effect transistors comprising a floating gate, provides a non-volatile storage mechanism with moderately high information density and low access times, it turns out that further device scaling and compatibility to other sophisticated mask technologies may be difficult to be achieved on the basis of conventional concepts for forming non-volatile storage transistors. Particularly, forming flash memory cells integrated with FinFET devices has not successfully been achieved in the past.
In view of the situation described above, the present disclosure provides (flash) memory cells with improved performance characteristics as compared to the art and integrated within the process flow of manufacturing FinFET devices.